The integration of electronic microchip devices such as resistors, capacitors, fuses, diodes and transistors on a silicon substrate is the basis for integrated circuit (IC) wafer fabrication technology. The most popular IC technology, CMOS (complementary metal-oxide semiconductor), revolves around the improvements that have been made in FET (field-effect transistor) design and fabrication.
The FET is a voltage-amplifying device. The greatest advantage of the FET is its low voltage and low power requirements. Two basic types of FET are the metal-oxide (MOSFET) semiconductor and the junction (JFET). MOSFETS have been the mainstay transistor in IC products. There are two categories of MOSFETs: nMOS (n-channel) and pMOS (p-channel). Each MOSFET has an input electrode called the gate. The term “metal oxide” refers to the material the gate is made of. The most popular material used in the formation of gates for MOSFETs is polycrystalline silicon material that is deposited on the substrate during IC fabrication. Polycrystalline silicon must be doped with one of the common p-type or n-type dopants to give the material its conductive characteristics.
SOI technology and the advantages attributed thereto regarding CMOS integrated circuits are well documented. SOI technology involves silicon wafers having a thin layer of oxide buried therein. Semiconductor devices are built into the thin layer of silicon on top of the buried oxide. SOI substrates provide superior isolation between adjacent devices in an integrated circuit as compared to devices built into bulk wafers, since SOI technology eliminates latch-up as well as reduces parasitic capacitances. CMOS ICs fabricated with SOI technology have less active current consumption while maintaining device performance equivalent to that of similar devices formed on bulk-silicon (bulk-Si) substrates. SOI technology has become increasingly more common as the demand for battery-operated equipment increases due to its low power requirements at high speeds of SOI devices.
Many different techniques exist regarding the formation of SOI wafers. One of the more popular methods used to fabricate SOI substrates is separation by implantation of oxygen (SIMOX). SIMOX involves implanting oxygen ions into the silicon substrate to form the buried oxide layer. Layer transfer which includes wafer bonding is another technique employed for forming an isolation layer in a substrate. Forming silicon islands through a series of etch and oxidation steps can provide a lateral isolation structure.
In standard MOSFET technology, both channel length and gate dielectric thicknesses are reduced to improve current drive and switching performance. The carrier mobility of a MOSFET device is a critical parameter as it has direct influence on output current, as well as switching performance. Consequently, one can increase device performance by enhancing the channel mobility. Such enhancement has been provided in certain devices by providing a strain to the silicon film. A net strain can be provided by either compressive stress of the silicon film or tensile stress of the silicon film. While there are many approaches to stress the silicon, the primary focus in the past has been on using abutting layers of nitride or other materials on the front end of the substrate. All of these have been direct etch/deposition approaches for SIMOX based SOI structures.
Further, many approaches to stress channels have primarily relied on creating the “same-sign” stress in the channel. In all these cases, the same-sign stress transfer occurs because the channel is in front of the film (for example, etch stop liner) edge. By “same sign” it is meant that the stress in the silicon channel will be tensile, if the film is tensile, and compressive, if the film is compressive.
In view of the above remarks, there is a need to provide a semiconducting device that combines the advantages of SOI technology with strain based device improvements.